This invention relates to data communication, and more particularly to circuitry for receiving data signals that have been communicated from a data signal source.
Data signals may be transmitted from source (or transmitter or TX) circuitry (employing a source circuitry clock) to destination (or receiver or RX) circuitry (employing a destination circuitry clock). Although nominally of the same frequency, there may be a slight difference in actual frequency between the source circuitry clock and the destination circuitry clock. The destination circuitry receives data at the source clock rate, but ultimately processes that data at the destination clock rate. If the source clock is slightly faster than the destination clock, the destination circuitry will ultimately not be able to keep up with the incoming data unless some provision is made for dealing with that type of situation. Similarly, if the source clock is slightly slower than the destination clock, the destination circuitry will occasionally run out of data to process and may therefore operate erroneously, again unless some provision is made to deal with that type of situation.
To address issues of this kind it is known to include “clock rate matching” circuitry in receiver (destination) circuitry. Clock rate matching circuitry is typically buffer circuitry such as a first-in/first-out (“FIFO”) memory. The FIFO stores received data at the TX (source circuitry) clock rate. The oldest, previously unread data in the FIFO is read out at the RX (destination circuitry) clock rate. If the FIFO is becoming too full, it is because the TX clock is faster than the RX clock. This is dealt with by deleting (e.g., not writing into the FIFO) a deletable item of data, such deletable (and therefore ultimately meaningless) items of data being occasionally included in the data stream for this purpose. (An “item” of data is typically the amount of data that would otherwise be written into the FIFO in one cycle of the FIFO write clock. For example, such an item of data may be a “byte” of eight or some other predetermined plural number of bits, or a “word” of two or some other predetermined plural number of bytes, or any other predetermined amount of data. For convenience herein such items of data will generally be assumed to be individual bytes, but it will be understood that this is only illustrative and that any other amount of data can be a deleted item (or an inserted item).)
Similarly, if the FIFO is becoming too empty, it is because the TX clock is slower than the RX clock. This is dealt with by inserting (e.g., reading again from the FIFO) an insertable item of data. Insertable items are again ultimately meaningless and may be the same as the above-mentioned deletable items.
Certain kinds of circuitry are intended to be multi-purpose. This is generally true, for example, for programmable logic devices (“PLDs”). It is generally desirable to design a PLD so that many different users can use it for a wide range of different uses. In this way, the PLD can be manufactured in large quantities, thereby lowering its unit cost. Certain ASIC architectures may also be designed so that with only limited customization they can support many different uses.
There are many different communication protocols that may require clock rate matching. For example, there are many different industry-standard protocols such as XAUI, Infiniband, Gigabit Ethernet, Fiber Channel, and Serial Rapid I/O, to name just a few. In addition, many users want to design their own communication protocols, which may deviate to a greater or lesser degree from some industry-standard protocol, or which may be quite different from any industry-standard protocol.
Multi-purpose clock rate matching circuitry is therefore needed, especially for inclusion in circuitry that is otherwise intended to be multi-purpose, to support the different clock rate matching needs of many different users.